1. Field of the Invention
Embodiments of the present invention generally relate using a graphics processor as a coprocessor to perform register transfer level simulations of an electronic circuit.
2. Description of the Related Art
Conventionally, cycle based simulations, such as register transfer level (RTL) simulations are performed by a general purpose processor (CPU). FIG. 1 illustrates a prior art computing system, host computer 100, for performing RTL simulations, including a CPU, host processor 110. A system interface 115 couples host processor 110 to a host memory 120. Host memory 120 stores an RTL model of an electronic circuit, device under test 125, a testbench 130, simulation results 135, and simulation input 140. Testbench 130 provides a framework for device under test 125, providing clock signals, reset, and identifying other inputs and outputs. An RTL simulation is performed when host processor 110 executes a simulation application program, electronic design automation (EDA) application 145, providing simulation input 140 to device under test 125 via testbench 130. Output signals are produced for each specified timestep and stored as simulation results 135. Simulation results 135 may be displayed using a waveform viewer application or other application.
RTL simulations require a significant amount of host processor 110 computing cycles, making host processor 110 less available to other applications. Accordingly, there is a desire to offload a portion of RTL simulations in order to improve overall system performance or to complete the RTL simulations in less time.